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Sheetal Nagar, Shanky saxena, Seema Nayak,Govind Singh Patel


Multiplication basically is the fundamental function of various applications in latest era.

In this era there is a rapid change in communication sector and medical sector to reduce power

and cost while no compromise with quality. Various applications are error tolerant where accuracy is not on the highest priority. A high power consumption results make the speed lower in the multipliers. In this work we present a review and comparison review  for the use of low approximate multiplier to resolve the issues of error tolerance applications such as Machine learning, IOT (Internet of thing), IIOT, FIR, DSP, IIR, and Image processing, signal Processing, Artificial Intelligence Image Shrinking, Image compressing and data mining and analysis. Valuable Schemes and various architectures of low power Multiplier are Analyzed or Compared for improvement of the parameters of low power multiplier like Power, Area, Delay, Speed and Energy. Simulation Tools which are mostly taken as priority by the researchers for the are Mat Lab, cadence, Xilinx and Verilog are used to improve the parameters with the design of latest architecture for low power multiplier.

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How to Cite
Sheetal Nagar, Shanky saxena, Seema Nayak,Govind Singh Patel. (2022). A COMPARATIVE STUDY ON APPROXIMATE LOW POWER MULTIPLER. Journal of East China University of Science and Technology, 65(4), 578–586. Retrieved from http://hdlgdxxb.info/index.php/JE_CUST/article/view/476